Assessment of SiGe quantum well transistors for DRAM peripheral applications

In this work, the potential of Si
_1-x
Ge
_x
Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of external resistance is observed for Si
_1-x
Ge
_x
Quantum Well devices, which is attributed to junction induced defects creation at the SiGe/Si buffer layer interface. This highlights the need for a dedicated junction solution in SiGe QW devices. The junction leakages are also investigated, and it is found that Band to Band Tunneling is the dominant mechanism setting the minimum Off-state leakage current. Band to Band Tunneling is increasing when the Ge content is increased, and it may effectively cap the allowed Ge channel content for Low Power Applications. The minimum Off state leakage requirement for DRAM peripheral applications is still obtained for a Ge concentration of 45%.