Silicon Nanowire Arrays Based On-Chip Thermoelectric Generators

Thermoelectric generators (TEGs) can improve the net power consumption of electronic packages by generating power from the chip waste heat. In this paper, a 3-D computational model of electronic package with silicon nanowire (Si-NW)-based embedded TEGs has been developed and the effect of crucial geometric parameters, contact resistances, and thermal properties, such as pitch length and length of Si-NWs, the electrical contact resistivity at Si-NW interface, thermal contact resistivity at TEG-package interface, and filling material thermal conductivity on power generation, has been evaluated. The analysis has shown how modifying some crucial parameters from their current values in different experimental studies affect power generation, e.g., decreasing the pitch length from 400 to 200 nm doubled the power generation, increasing the Si-NW length from 1 to 8 μm increased power generation by a factor of three and decreasing contact resistivity by one order of magnitude from 1.0×10
^-11
Ω · m
²
enhanced the power generation by a factor of two. This paper has estimated the energy conversion efficiency of 0.15% for 8-μm long Si-NWs using the best thermoelectric properties available from different experimental studies. Finally, performance of Si-NW-based TEG has been compared against the Bi
₂
Te
₃
superlattice-based TEGs and the crucial parameters of Si-NW TEGs have been identified which should be the focus of the future studies.