Innovative Variable Mesh Simulator

A valuable design to aid designers of digitial computer circuits is a "good" logic simulator. Because the digital hardware technology has advanced rapidly over recent years (i.e., more and more logic gates on a single chip), faster and easier to use logic simulators capable of handling large, complex digital circuits are continually in demand. An important milestone in meeting this demand was the development of the Innovative Variable Mesh Simulator (IVMS). The IVMS program is based on the flat model approach and permits interactive or batch processing. An earlier logic simulator called the Variable Mesh Simulator (VMS) is based on the hierarchical model approach and only permits batch processing. The use of the flat model approach in IVMS instead of the hierarchical approach in VMS results in a faster simulation for the same application. In addition to the processing advantages, interactive IVMS provides logic designers with the means to debug within a short period of time both the test case problems and the structure (the overall design and/or the behavior models). IVMS permits the user to explore various model changes and/or stimuli changes with the resulting output effects while in, the same session. A more detailed description of the IVMS program development is given in this paper, including a comparsion of the flat model and hierarchical models' approaches of simulator construction. The key features of the MS program, including some examples of performance data, are also described.