Quasi-universal VLSI multiplier with signed digit arithmetic

This paper presents techniques to increase the speed and improve the VLSI suitability in designing fixed-point multipliers. The implementation of high-speed multiplication algorithm using redundant binary addition tree has been investigated and a minimal logic design of Redundant Binary Signed-Digit (RBSD) adder cell is presented. The regular interconnects on structures of these adder cells result in a multiplier which is ideal for VLSI implementation. The increased speed is achieved through carry free addition of partial products using redundant signed-digit numbers. The use of multiplier recoding scheme with a group size of three, which will reduce the number of rows in the partial product matrix by a factor of three, is discussed. The complexity introduced by this recoding scheme is the need for multiples of -3 and +3 of the multiplicand which involves carry propagation free adders for these precalculation units in conventional designs. This scheme results in a significant improvement in speed and is very efficient for multipliers with large operand lengths.