A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration

Large-scale workloads often show parallelism of different levels. which offers acceleration potential for clusters and parallel processors. Although processors such as GPGPUs and FPGAs show good performance of speedup, there is still vacancy for a low power, high efficiency and dynamically reconfigurable one, and coarse-grained reconfigurable architecture (CGRA) seems to be one possible choice. In this paper, we introduce how we use our CGRA fabric Chameleon to realize a dynamically reconfigurable acceleration to MapReduce-based (MR-based) applications. A FPGA-shell-CGRA-core (FSCC) architecture is designed for the acceleration PCI-Express board, and a programming model with compilation flow for CGRA is presented. With the supports above, a small evaluation cluster with Hadoop framework is set up, and experiments on compute-intensive applications show that the programming process is significantly simplified, with an 30-60
$\times$
speedup offered under low power.