A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation

This paper presents a fully integrated process, supply voltage, and temperature compensated supply (PVTCS) for a point-of-load digital system. Through adding the appropriate weighted threshold voltage variation from the pMOS (ΔV
_THP
) and the nMOS (ΔV
_THN
) diodes to the reference voltage of a high-speed low-dropout voltage regulator, the supply of the digital circuit becomes adaptive, and hence, it minimizes the speed deviation in the context of PVT variations. Validated in a UMC 65-nm CMOS process, the simulation and the measurement results of an inverter chain-based oscillator have validated the effectiveness of PVTCS. It can significantly reduce the delay variations with respect to the uncompensated supply counterpart. The same goes for a sample critical path-based oscillator with extensive simulation results. Therefore, the proposed circuit is useful for the digital point-of-load application, with the key technical merit of PVT compensation without encountering the potential latch-up problem from the reported methods.