Experimental and numerical investigations on Cu/low-k interconnect reliability during copper pillar shear test

In this work, innovative experiments and failure analysis during copper pillar shear test are described and complemented with simulation. The aims are to, firstly, establish several copper pillar bump failure scenarii and look into the alleged failure mechanisms involved during the shear test. It is accomplished experimentally by carrying out incremental tests on a 28nm CMOS technology test chip. More precisely, the shear tool is stopped at various stages during the test, and the subsequent FIB/SEM cross-sectional views are performed. Three main distinct modes are highlighted and discussed. The second aim of this paper is to investigate the design and layout effects (i.e. copper density in interconnect levels). To do so, different BEoL metallization densities are studied experimentally and numerically. During this dedicated campaign, the three aforementioned failure modes are also observed. Focusing on the cratering mode, which underlines a weakness at the BEoL level, experiments reveal that structures having the lowest metal density are more prone to fail than the balanced ones. Then, simulations are performed to give deeper understanding. Good agreement is found with the experimental observations, which highlights the impact of the BEoL structure on the reliability. Lastly, this work provides a comprehensive understanding of the BEoL behavior under bump shear loading, and enables further design optimization to secure assembly processes of advanced semiconductor technologies.