A comprehensive reliability study on a CoWoS 3D IC package

Assembly of stacked die side by side on a passive interposer enables high-bandwidth connectivity between multiple die by providing a significantly large number of die to die connections that otherwise are not possible in a multi-chip-module (MCM) configuration. It also provides much lower latency and consumes dramatically lower power than either the multiple FPGA or MCM approach. This enables integration of massive quantities of interconnect logic, transceivers, and on-chip resources within a single package. However, this also poses critical challenge of testing the reliability of inter die connections during board level testing. Traditionally, flip chip reliability evaluations use independent component and board level methods to capture various failure modes. The board level method is often a simple daisy chain test method that targets the Ball Grid Array (BGA) solder balls. The component level test captures the C4 and active circuitry but ignore BGA and the effect of board mounting assembly process. Given complexities in terms of geometry, material and assembly process, 3D IC packages are more sensitive to warpage changes. Small changes in warpage can have a significant reliability impact on the thin interposer as well as the stacked silicon. A unified test methodology that can test the top FPGA die, inter die interconnections, TSV, C4 bumps and BGA connections while being mounted on a board is the most comprehensive method for performing reliability evaluations on a 3DIC package, much like an end user/customer would see in their application. This paper presents a novel methodology and results of a comprehensive functional board level reliability evaluation on a 3D IC package assembled using Chip on Wafer on Substrate (CoWoSTM) process. The comprehensive reliability evaluation method discussed in this paper uses a specially designed test board for mounting the functional device. The test board much like a probe card provides access to active circuitry in the stacked silicon. This enables identifying any small silicon crack , Low-K delamination or degradation in the active silicon. Additionally the test board also provides access to 85000 die to die microbump interconnections. Having access to the microbump is very important as they form 80% of the interconnections and more susceptible to failure due to their geometry and material complexities. Finally, all other general purpose IO's can also be tested much like a daisy chain board level vehicle. The reliability of the CoWoS 3DIC device mounted on the board was tested for various high temperature storage and thermal cycling test conditions for beyond JEDEC requirements. The comprehensive test methodology was effective in capturing various failure modes and their interactions. The results of this study have clearly demonstrated the robustness of the CoWoS 3D IC device. The packages and FPGA die survived extended tests well beyond the JEDEC test requirements.