Comparative study regarding two implementations of an SEC-DED code with FPGA circuits

In this paper we compare two different implementation of an SEC-DED HSIAO code. This comparison is made to select which is the best method to achieve better memory, from reliability point of view. In this paper HSIAO code is used, because is efficient for single errors correction and double error detection that appear in cache memory hierarchy. Also, we have implemented the HSIAO code with FPGA Xilinx circuits for both implementations.