Implementation of a DSSS modem ASIC chip for wireless LAN

This paper presents a high-speed DSSS (direct sequence spread spectrum) modem ASIC chip for wireless local area network (WLAN). The implemented modem chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip supports various data rates, i.e., 4 Mbps, 2 Mbps and 1 Mbps and provides both DBPSK and DQPSK for data modulation. We have simulated algorithm models using the SPW/sup TM/ and verified the BER performance in AWGN channel environments. Moreover, we have verified the BER performance for the carrier frequency offset and clock offset under the AWGN channel environments. We have simulated the architecture using VHDL models and have performed logic synthesis using the SYNOPSYS/sup TM/ v3.4a design analyzer. The chip has been fabricated using the 0.6 /spl mu/m gate array library (KG75) and consists of 53,355 gates and operates at 44 MHz. The implemented architecture shows lower BER than the Harris HSP3824.