Modeling, Fabrication, and Reliability of Through Vias in Polycrystalline Silicon Panels

Silicon interposers with through-silicon vias (TSVs) have been developed in single-crystalline silicon wafer to address the high I/O density requirements between high performance logic, memory, graphic, and other devices. However, single-crystalline silicon interposers suffer from many shortcomings such as high cost, low electrical performance, and reliability. To overcome these shortcomings of traditional silicon interposers, an entirely different approach using polycrystalline silicon panels with polymer liners and through-package-vias (TPVs) is proposed by Georgia Tech Packaging Research Center. This paper, for the first time, focuses on the reliability of TPVs in polycrystalline silicon interposers fabricated from panels. Mechanical simulations were carried out that show lower stresses in TPVs in polycrystalline silicon lined with thick polymer liners, compared with TSVs in traditional single-crystalline silicon with thin SiO
₂
layers. TPVs were fabricated for thermal cycling tests, resistance monitoring, and scanning electron microscope imaging. The reliability characterization results showed good mechanical reliability of TPVs in polycrystalline silicon panels.