Range-Enhanced Packet Classification Design on FPGA

The future of fast Internet needs powerful routers to support abundant network functionalities, such as firewall, QoS, and virtual private networks, by classifying the packets into different categories based on a set of predefined rules, so-called multi-field packet classification. Traditional packet classification that considers only 5-tuple fields is not sufficient for today's complicated network requirements. OpenFlow switch was born to take care of these complex requirements using a rule set with the rich definition as the software-hardware interface. This paper considers OpenFlow1.0, consisting of 12-tuple header fields. We propose two schemes to process the range fields. The first scheme has the same characteristic as StrideBV [15] using specially designed codes to store the pre-computed results in memory. The second scheme uses a simple sub-range comparison method to find the matching result in a sequential fashion. To show the performance and compare with other proposed schemes, we implement the proposed schemes on Xilinx Virtex-6 XC6VLX760 FPGA device. Experimental results show that our designs can handle 5 K more OpenFlow rules on Virtex-6 XC6VLX760. To the best of our knowledge, our proposed scheme is the first range supported method that can sustain the throughputs of more than 380 MHz.