An analog integrated circuit of a Hamming neural network designed and fabricated in CMOS technology

An analog integrated circuit of a Hamming neural network designed and fabricated in CMOS technology is presented. The template matching calculation circuit in the neural network is composed of distributed neurons formed by pull-up and pull-down CMOS transistor pairs. A multiple input and output "winner take all" network is designed in pseudo NMOS circuit. Testing results show that the Hamming network can work at high speed, and the "winner take all" network has a high resolution accuracy.