Tackling the complexity of exact path delay fault grading for path intensive circuits

The high accuracy of the Path Delay Fault model (PDF) is usually sidelined by its high complexity since the number of possible faults can become exponential to the circuit size (even when only critical faults are considered). Thus, fault simulation may require prohibitively large memory resources. In this work we propose a test reordering technique to control the complexity of exact PDF grading when Zero-suppressed Binary Decision Diagrams are used for fault representation. Experimentation on path dense benchmark circuits demonstrates considerable reduction in memory requirements for the PDF grading problem.