Multitime Programmable Memory Cell With Improved MOS Capacitor in Standard CMOS Process

A multitime programmable memory cell with improved MOS capacitor is proposed in this paper. The improved MOS capacitor has p-type junction near the channel, which prevents the capacitor from deep depletion, and this helps to improve the cell's program/erase efficiency and stability. A test chip is fabricated using a 0.13-μm standard CMOS process without any extra masks or process modification. The experimental results show that the proposed cell achieves much faster and more stable program/erase speed than do the cells using the conventional MOS capacitor. Furthermore, endurance characteristics of up to 10-k cycles and data retention at 250 °C are presented, and the results indicate that the improved MOS capacitor does not affect the cell's reliability.