Automated test pattern generation for VHDL codes of VLSI chips

Summary form only given, as follows. This paper introduces a methodology for automated test pattern generation (ATPG) for VHDL codes of VLSI chips. A VHDL specification of a VLSI chip can be modeled as a data flow graph based EFSM (Extended Finite State Machine). The EFSM model is then checked for any of the three types of defined consistencies. Techniques available for finite state machines (FSM) testing can then be used to generate test patterns for the consistent EFSM model (with all inconsistencies detected and removed). Algorithms are being developed and coded for detection and removal of inconsistencies and for optimized test pattern generation for the consistent EFSM. Examples are used to introduce and explain the processes, algorithms and tools used in this project.