Simulated fabrication of heterojunction bipolar transistors using process technology CAD tools

Process simulation is not widely used to date in the compound semiconductor industry owing in part to several issues that exist in applying commercially available simulation tools designed for silicon integrated circuits to the fabrication of III-V-based devices. These issues arise from the inherent differences in the fabrication techniques used in the separate device technologies. Computer simulations have been applied to model heterojunction bipolar transistor (HBT) fabrication at HRL laboratories. These silicon based simulations require calibration to accurately model the profiles produced during III-V device and IC fabrication. The calibration method includes the use of silicon processing techniques to produce simulated cross-sections which are then compared with focused ion beam cross-sections of actual devices. To our knowledge this is the first reported simulation of InP-based HBT fabrication for high density circuit applications.