Hardware Acceleration of Online Error Detection in Many-Core Processors

Due to worsening aging effects and incomplete testing and verification processes, systems being built in new fabrication technologies have encountered serious reliability challenges. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this paper, a scalable self-test mechanism for online testing of many-core processors has been proposed. Several hardware components are incorporated in the many-core architecture that distribute software test routines among the processing cores, monitor behavior of the processing cores during test routine execution, and detect faulty cores. A merit-based probabilistic test generation (MPTG) method to generate test for register-transfer level components considering the limitations imposed by the neighboring components has been proposed. In addition, a test generation approach utilizing MPTG has been proposed for software test routine generation in this environment. Experimental results show that the proposed test generation method results in good stuck-at fault coverage in a limited number of test cycles. In addition, the proposed test mechanism is extensively scalable in terms of hardware and timing overhead making it applicable to many-cores with a large number of processing cores.