Review on FFT architecture for real valued signals using Radix 25 algorithm

A novel approach to develop a Fast Fourier Transform (FFT) for real valued signal using Radix 2⁵ algorithm is proposed in this paper. Methodology is to modify the flow graph of the FFT architecture. Redundant components are replaced by the imaginary computations. Hardware complexity of this RFFT architecture will be low compared to Radix 2³ and Radix 2⁴ algorithms in terms of adder, multiplier and delay. This proposed architecture maximizes utilization of hardware with no redundant computation. RFFT is used for real time applications and also in portable devices where low power consumption is the main requirement. So accordingly vedic multiplier and carry save adder has been used in the proposed work.