VLSI design of a parallel architecture 2-D rank order filter

A VLSI parallel architecture implementing a new algorithm for 2-D rank order filtering, based on repeated maximum finding operations, is presented in this paper, and the design of a programmable demonstrator chip realised in standard-cell 1 μm CMOS technology is described. The chip has programmable window size and selectable rank, it can work with unitary throughput at 25 MHz, in the worst case, and its area is 7 × 5.5 mm
²
.