High level synthesis for designing custom computing hardware

We apply High Level Synthesis (HLS) to the design of FPGA based computing systems. HLS allows for a level of design space exploration unrealizable with Register Transfer Level (RTL) techniques. The use of HLS tools allow designers to prototype their designs with high quality results and fast turn around times. Our design flow makes use of Synopsys Behavioral Compiler (BC) followed by logic synthesis to map designs onto the Altera RIPP10 board. We illustrate our approach with a case study: the design of a DTMF receiver from a high-level behavioral description down to implementation on the RIPP10 board. We were able to design working hardware, meet our delay constraints and achieve 90% utilization of the available FPGAs. The final design had approximately 90000 gate equivalents.