An 8×8 RLS based MIMO detection ASIC for broadband MIMO-OFDM wireless transmissions

This paper presents the architecture and VLSI implementation of a highly flexible MIMO detection engine which supports a wide array of configurations ranging from 1 × 1 to 8 × 8 square, as well as all possible non-symmetric MIMO configurations. The chip is specifically designed to work with an underlying OFDM modulation scheme, and covers the range of 64 to 1024 subchannels. It implements an RLS based MIMO solution which provides a good balance between hardware complexity and overall system performance. To further reduce the complexity frequency domain linear interpolation is also used. The actual implementation is based upon the highly scalable inverse QR decomposition based systolic array architecture. A single systolic array is time-multiplexed for all OFDM subchannels. This naturally overcomes the pipelining difficulty inherent in traditional single channel systolic arrays without doubling the array size. In conjunction with the array design, a unique input tagging scheme is incorporated to allow dynamic reconfiguration of the ASIC on a per packet basis, and also to reduce power consumption when only a sub-array is needed for the operation. The final implementation of the MIMO detection engine can support configurations as large as 8 × 8 in 12.5 MHz of bandwidth, or a 4 × 4 or any smaller array at up to 25 MHz of bandwidth. The chip was fabricated using a 3.3V/1.8V 0.18.um CMOS technology. The resulting core layout measures 29.2mm
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and clocks at a maximum frequency of 58MHz. In 2 × 2, 25 MHz configuration, it consumes 360mW, whereas in 12.5 MHz, 8 × 8 mode it consumes 830m W.