A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications

A new fast low-power flip-flop, called pulse-triggered TSPC flip-flop (PTTFF), is proposed. PTTFF uses a conventional latch structure clocked by a short pulse train, and it indeed acts as a flip-flop. The new flip-flop uses only 5 MOS transistors with only one transistor being clocked. Both the total transistor count and the number of clocked transistors per flip-flop are reduced to save the power consumption of the flip-flop itself and the clocking system. For a pipelined FIR macro, utilizing the proposed PTTFF can save up to 63% of power consumption of the clocking system. PTTFF can also operate very fast. The maximum toggle rate of PTTFF can be as high as 3 GHz if designed in a 0.6 /spl mu/m CMOS technology.