Integration of multi-level copper metallization into a high performance sub-0.25 /spl mu/m CMOS technology

A high performance sub-0.25 /spl mu/m CMOS technology has been developed with six levels of planarized copper interconnects. 0.15 /spl mu/m transistors (L/sub gate/=0.15 /spl mu/m) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects to minimize wiring induced RC delays.