A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing

A test chip has been fabricated in a fully depleted SOI CMOS process with 0.25-/spl mu/m drawn gate length, It successfully demonstrates the types of circuits required to perform digital filtering, detection, and data thinning functions at high clock speeds. The test chip contains over 5000 transistors and was clocked at speeds up to 1.3 GHz. A target application for these circuits is a very wideband compressive receiver for real-time spectral analysis, which requires digital signal processing to be performed on a 20-Gb/s data stream formed by digitizing a stream of fast analog pulses. Adjustable high-speed on-chip clocks, input and output registers, and large decoupling capacitors allowed testing of the chip to be performed using an inexpensive, low-speed probe card and a standard wafer prober.