A cost-effective three-step hierarchical search block-matching chip for motion estimation

A dedicated cost-effective chip of a three-step hierarchical search (3SHS) motion estimator to support the NTSC resolution video in real time is proposed. The memory interleaving technique is developed to overcome the 3SHS's inherent problem of complicated data addressing and interconnection due to the variable distance between candidate locations and unpredictable data requirements. Based on a cyclic-pipeline utilization of memory, the memory size and bandwidth requirements can be reduced significantly. With 0.8 /spl mu/m CMOS technology, the proposed chip requires a die size of 6.9/spl times/5.9 mm/sup 2/ with 120 K transistors, and is able to operate at a clock rate of more than 50 MHz.