A low-power VLSI design methodology for high bit-rate data communications over UTP channel

Presented in this paper is a systematic methodology to design low-power integrated transceivers for broadband data communications over unshielded twisted-pair (UTP) channels. The design methodology is based upon two algorithmic low-power techniques referred to as Hilbert transformation and strength reduction and a high-speed pipelining technique referred to as relaxed look-ahead transformation. Finite-precision requirements and power savings are presented. The application of these techniques to design low- and high-speed 155.52 Mb/s ATM-LAN and 51.84 VDSL transceivers is illustrated.