Technology and circuit optimization of resistive RAM for low-power, reproducible operation

Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaO
_x
/HfO
₂
/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.