A recursive switched-capacitor decimation filter design for 0.8 /spl mu/m CMOS technology

This paper presents the design steps considered in the development of an integrated circuit for a switched-capacitor decimation filter. The design consists of dimensioning the operational amplifiers, capacitances and analog switches, using a supply voltage of 5.5 V for a 0.8 /spl mu/m technology. Also shown are electrical simulations using PSPICE 5.0 considering both typical and worst case conditions for practical application in telecommunication systems, for a sampling rate reduction from 48.20 MHz to 16.07 MHz. The filter dissipates approximately 46 mW (including the output buffer) at 5.5 V, and presents a flat frequency response within 0.12 dB from dc to 3.56 MHz.