SILC-related effects in flash E/sup 2/PROM's-Part II: Prediction of steady-state SILC-related disturb characteristics

For Part I see J. de Blauwe et al., vol.45, no.8, pp.1745-50 (1998). In this paper, a new methodology is developed, and applied thereafter, to predict the disturb characteristics of an arbitrary Flash E/sup 2/PROM device which are related to steady-state stress induced leakage current (SILC). This prediction methodology is based on a quantitative model for steady-state SILC, which has been developed on capacitors and nFET's as was reported earlier in Part I. Here, this model is shown to be also valid for tunnel oxide Flash E/sup 2/PROM devices, and used thereafter in a consistent and well-understood cell optimization procedure. The model requires as only input basic cell parameters and an oxide qualification obtained at the capacitor and transistor level.