Back-Gate Effect on $R_{\mathrm {{\mathrm{{\scriptscriptstyle ON}},sp}}}$ and BV for Thin Layer SOI Field p-Channel LDMOS

The Backgate (BG) effect on specific ON-resistance (R
_ON,sp
) and breakdown voltage (BV) for the thin layer Silicon On Insulator (SOI) field p-channel lateral diffusion MOS (pLDMOS) are investigated in this paper. BG-induced dual conduction mode for the thin layer SOI field pLDMOS is revealed, which includes drift and accumulation conduction. Hole accumulation layer induced by BG voltage (V
_BG
) provides extra charges, resulting in a R
_ON,sp
reduction. An expression of equivalent R
_ON,sp
is given to describe the dependence of R
_ON,sp
on VBG. Simultaneously, VBG impacts strongly on BV, inducing three breakdown mechanisms: surface breakdown, bulk breakdown, and punchthrough breakdown. For surface breakdown, a positive linear dependence of BVs on VBG is given with consideration to multiple field plates (MFP). BV of -366 V and RON,sp of 7.5 Ω · mm
²
for the thin layer SOI field pLDMOS are achieved experimentally at V
_BG
= -200 V.