A CMOS current-mode pipeline ADC using zero-voltage sampling technique

A low-voltage low-power CMOS current-mode pipeline ADC is presented. Zero-voltage sampling technique and regulated cascode circuits are combined in the sample-and-hold circuits to increase the resolution. Dynamic latched-type comparators are used to implement high-speed low-power sub-ADCs. The multiplying DAC and the comparators are used with a digital error correction (DEC) circuit to realize a low-voltage low-power current-mode pipeline ADC. Simulation shows that the ADC can work at 20 MHz with an 8-bit resolution. The power consumption is 22 mW.