Clock skew reduction in ASIC logic design: a methodology for clock tree management

This paper presents a methodology for the automatic generation of clock trees in an ASIC design at the gate level. New algorithms and heuristics are described: they have been inserted with success in an industrial ASIC design flow, after the logic synthesis and optimization step. Our algorithms, by different heuristic methods, particularly take into account those elements connected as transmitter-receiver couples which represent the most critical configurations for circuit synchronization. Improvement of clock tree performance has also been obtained by means of an interaction strategy between logic and physical design phases. Such a strategy drives the placement of the clock tree elements in an equidistant way, in order to obtain a controlled routing.