Fault list compression for efficient analogue and mixed-signal production test preparation

Accurate test effectiveness estimation for analogue and mixed-signal Systems on Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. In this paper we present a novel fault list compression technique that defines a stratified fault list, build with a set of representative faults (RFs), one per stratum. Criteria to partition the fault list in strata, and to identify RFs are presented and discussed. A fault representativeness metric is utilized, which is based on an error probability. The proposed methodology allows a tradeoff between fault list compression and fault representation accuracy that may be optimized for each test preparation phase. The methodology is independent of the chosen fault models and it is tested on cells with and without feedback. Fault representativeness evaluation is presented by applying the methodology to an industrial DC-DC converter. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.