Gate-drain capacitance behaviour of the DMOS power transistor under high current flow

The gate-drain capacitance of a power DMOS transistor was measured under high current conditions of up to 250 A. Depending on V/sub GS/ a strong nonlinear characteristic was observed. Using the measured capacitance data the characteristics of the inner MOS transistor and the epi region have been determined separately for parameterisation and modelling.