A 3.3 V 600 MHz-1.30 GHz CMOS phase-locked loop for clock synchronization of optical chip-to-chip interconnects

A high-speed phase-locked loop for clock synchronization of optical chip-to-chip interconnects has been developed. It consists of a photo-diode, an amplifier, a phase detector, a charge pump, a loop filter, and a voltage control oscillator. In order to make our phase-locked loop operate in optical interconnects efficiently, we apply an improved fully integrated CMOS photo-detector, and propose a new phase-locked loop with a high-speed three-state phase detector and a wide-range voltage control resistor. The proposed phase-locked loop has been implemented by using the UMC 0.5 /spl mu/m CMOS technology with a die size of 300 /spl mu/m/spl times/400 /spl mu/m. The HSPICE simulation results show that the optical signals from 1.2 Gb/s (600 MHz) to 2.6 Gb/s (1.3 GHz) can be locked at a supply voltage of 3.3 V. The jitter of proposed phase-locked loop at 1 GHz is less than 15 ps. Its power consumption is around 150 mW. Therefore, our phase-locked can be widely used in high-frequency and low-power optical chip-to-chip interconnect systems.