Test method for IC electrical overstress hardness estimation

A test method to estimate the electrical overstress (EOS) hardness of ICs is presented. It is based on unification of test conditions. The advantage of the method is the possibility it gives to compare the EOS hardness of different ICs. A specialized test installation has been designed to estimate the hardness of different ICs to EOS, including transient and permanent effects. Experimental data for digital bipolar IC and 4K/spl times/1 CMOS RAM EOS hardness are given including the effects of upset, latch-up and catastrophic failure.