Logical Effort model for CNFET-based circuits

Carbon Nano-Tube Field Effect Transistors (CNFETs) are considered to be a promising candidate beyond the conventional CMOSFET. It is due to their higher current drive capability, ballistic transport, lesser power delay product and better thermal stability. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs determine current driving capability, speed, power consumption and area of circuits. Logical Effort (LE) technique is used for quick and accurate estimation of delay in large CMOS circuits. Due to specific to CNFET parameters LE technique developed for CMOS cannot be directly transferred to CNFET circuits. We present a newly developed Logical Effort model for CNFET-based circuits that includes influence of CNFET specific parameters. Our model results in fairly accurate delay estimation with an average error around 5% for a set of tested CNFET circuits. The inclusion of CNFET technology parameters in the model ensures the scalability of the model with technology nodes.