A Novel Quasi-3D Interface-Trapped-Charge-Degraded Threshold Voltage Model for Omega-Gate $(\Omega{G})$ MOSFETs

With the effects of equivalent oxide charges on the flat-band voltage, we report a novel quasi-3D interface-trapped-charge-degraded threshold voltage model for omega-gate (ΩG) MOSFETs based on the quasi-3D scaling equation, including the equivalent number of gates. It is found that a thin gate oxide is required to reduce threshold voltage degradation by the trapped charges. For the positive/negative trapped charges, the damaged device with a thick/thin silicon film suffers from small/large threshold voltage degradation. In addition, a large/ small oxide-to-gate underlap coverage factor can be adjusted to improve the threshold voltage degradation by the positive/negative trapped charges. For the short-channel behavior, a damaged device with the negative trapped charges is better than the one with the positive trapped charges. The model can be used to explore the hot-carrier-induced threshold voltage degradation of the ΩG MOSFET for its memory cell application.