Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders

In order to simplify the check node operation of the low-density parity-check (LDPC) decoders, this paper presents a Normalized Probabilistic Min-Sum Algorithm (NPMSA), where the second minimum value is replaced by a probabilistic second minimum value. For NPMSA, the number of required comparisons can be reduced to about half compared to that of the conventional Normalized Min-Sum Algorithm (NMSA). It is shown that the simplification only introduces negligible impact on the bit-error rate performance, especially for codes with a high check node degree. When the proposed NPMSA is applied to the (2048, 1723) RS-LDPC code, the degradation in the error-rate performance is only about 0.05 dB. The hardware implementation shows that a throughput of 45.42 Gbps can be achieved using the proposed NPMSA.