Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection

A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS ICs without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCRs or PCLSCRs has a tunable holding voltage greater than VDD of the ICs. Such cascode NCLSCRs (or PCLSCRs) can provide the CMOS IC's with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCRs (PCLSCRs) design has been practically applied to protect the ICs in a 0.35 /spl mu/m silicide CMOS technology with the HBM ESD robustness above 3 kV.