A 325 MHz 3.3 V 10-bit CMOS D/A converter core with novel latching driver circuit

This paper describes a very compact 10-bit D/A converter (DAC) core which achieves 325 MHz operation with a 3.3 V analog supply. A double cascoded p-channel current source array with a 5 bit MSB segmented and 5 bit LSB binary architecture results in less than 1 LSB of DNL/INL and sub-nsec rise/fall times. A novel latching driver circuit combines the digital decoding latch and switch driver functions into a single circuit. The die area is 0.135 mm/sup 2/, less than 1/10 the size of previously reported 8-bit DAC designs.