Architecture and implementation of a bitserial sorter for weighted median filtering

A new flexible architecture of a sorter for weighted median filtering based on the odd/even-transposition algorithm is presented. The bitserial approach supports variable word lengths for input samples and weights. The architecture is scalable with respect to the window size, as well as to the throughput rate, and silicon area for different signal processing applications. It is well suited for a datapath generator assisted design of full-custom macros from a very small set of optimized handcrafted leaf cells. The required leaf cells for different filter applications were implemented and allow a clock frequency of 200 MHz, using a 0.5 /spl mu/m CMOS technology.