A new scalable VLSI architecture for Reed-Solomon decoders

A scalable VLSI architecture for Reed-Solomon decoding suited for data rates from 10 Mbit/s to 1.2 Gbit/s in a 0.5 /spl mu/m-CMOS technology is presented. New regular, time-shared architectures have been derived for solving the key equation and performing finite field divisions. A small silicon area in comparison with state-of-the-art decoder implementations demonstrates the efficiency of the proposed architecture.