Semi-recursive VLSI architecture for two dimensional discrete wavelet transform

This paper presents an efficient two-dimensional discrete wavelet transform (2-D DWT) VLSI architecture which calculates the 2-D DWT for image processing in real-time. The proposed architecture, semi-recursive 2-D DWT VLSI architecture, has the minimum H/W cost of internal word length, data-bus utilization, scheduling control overhead and storage size. Compared with the conventional recursive 2-D DWT VLSI architecture, the size of multipliers and registers are reduced by 13% and 34% respectively. Furthermore, the semi-recursive 2-D DWT VLSI architecture exploits the lapped block processing and hence has the minimum transposition storage size and short latency.