AXI-based SpaceFibre IP core implementation

The steadily increasing demand of high-throughput interfaces, e.g., in satellite payload processing systems, drives the development of faster data transmission systems. The emerging SpaceFibre standard offers a multi-gigabit serial connection which is specified on the physical and data link layer while reusing the SpaceWire protocol specification on the higher protocol layers, thus enabling compatibility on the software layer. The AXI SpaceFibre IP core presented in this paper combines the SpaceFibre CODEC IP core developed by STAR-Dundee, a TLK2711 WizardLink Transceiver (meeting the SpaceFibre specification with up to 2.7 Gbit/s), and a DMA interface that connects the IP core to any AXI-based reconfigurable system-on-chip using FPGAs. The IP core configuration and initialization registers for the SpaceFibre RX and TX channels are accessible via AXI4-lite slave interfaces while the payload data is handled by a dedicated scatter/gather AXI-DMA core, which is connected to AXI-Stream FIFOs to provide the maximal possible payload transaction performance. The SpaceFibre IP core can be configured to implement 1 to 8 virtual channels. To evaluate the performance of the SpaceFibre IP core, we integrated it into the “Dynamically Reconfigurable Processing Module” (DRPM), a multi FPGA platform for satellite data payload processing. The AXI-based SpaceFibre IP core was synthesized on a Xilinx Spartan-6 LX150, utilizing in total 2668 slices and 36 BRAMs. For data segments larger than 1 kByte, a bandwidth of approximately 1.9 Gbit/s was achieved, corresponding to 95 % of the possible bandwidth. The IP core will be part of the ESA IP core repository.