2.4 Gb/s GaAs 8*8 time multiplexed switch integrated circuit

A 2.4-Gb/s GaAs 8*8 matrix switch for high-speed digital communication services has been designed, fabricated, and tested. The reconfiguration rate was designed to be at the data rate. A self-aligned refractory gate heterostructure FET technology (depletion mode) was chosen to implement the switch chip. The switch fabric was implemented in transmission gates to suppress crosstalk, minimize delay, minimize space, and lower power dissipation. The BFL (buffered FET logic) family was chosen for the logic gates. The 8*8 switch was designed to be nonblocking and provide multicast capability.<
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