A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter

This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analog-to-digital converter (ADC) with 20-nm gate length. Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. Signal-to-noise and distortion ratio is 31.4 dB for the HTFET SAR ADC, which is 2.81 dB higher than the Si FinFET ADC due to the decreased quantization noise rising from the high ON-current characteristic of HTFET at low supply voltage. The energy per conversion step for both HTFET and Si FinFET ADC designs are 0.43 and 1.65 fJ/conversion-step, respectively, at a fixed supply voltage of 0.30 V.