FPGA based hardware implementation of a self-organizing map

An embedded parallel pipeline solution for hardware implementation of Self Organizing is discussed. The Kohonen Self Organizing map was successfully applied in the travelling salesman problem for a robotic mobile agent application. The theoretical background of the application was discussed in a pre-study [1], current paper focusing on hardware implementation of the self-organizing map. The strength of the solution presented in the paper results from the parallel-pipeline architecture and the parallel computation of the output and the weight update. On hardware implemented processing units the SOM neurons are processed sequentially. Solution for parallel processing of the network output and weight update based on use of dual port BRAM memory, which enables to read and modify the values of the weights in same clock cycle, is presented. The number of hardware neurons used depends on the resources of the used FPGA. From the hardware implemented neural network an IP core was generated and integrated to a Microblaze processor bus system, enabling the programming of the system parameters and testing the system in real applications.