An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip

Networks-on-Chip (NoC) have emerged as communication backbones for enabling high degree of integration in future many-core chips. Despite their advantages, the communication is multi-hop and causes high latency and power dissipation, especially in larger systems. Wireless Network-on-Chip (WNoC) significantly improves the latency over traditional wired NoCs for multi-core systems. But on-chip wireless interfaces (WIs) have their own power and area overhead. In this paper we design and implement a Dynamic Voltage Frequency Scaling (DVFS) technique and extend it to provide power gating to the WIs. This approach effectively reduces the energy consumption in multi core systems. A centralized controller with dual-band wireless transceiver implements per-core DVFS. The scheme ensures balanced workload and energy consumption of the chip and efficient power gating for the WIs. It helps to alleviate the power consumption up to 33.085 % for on-chip communications infrastructure with little overheads.